IBIS Macromodel Task Group Meeting date: 15 July 2008 Members (asterisk for those attending): Ambrish Varma, Cadence Design Systems Anders Ekholm, Ericsson * Arpad Muranyi, Mentor Graphics Corp. Barry Katz, SiSoft * Bob Ross, Teraspeed Consulting Group Brad Brim, Sigrity Brad Griffin, Cadence Design Systems David Banas, Xilinx Donald Telian, consultant Doug White, Cisco Systems Essaid Bensoudane, ST Microelectronics Fangyi Rao, Agilent Ganesh Narayanaswamy, ST Micro Gang Kang, Sigrity Hemant Shah, Cadence Design Systems Ian Dodd, Agilent Joe Abler, IBM * John Angulo, Mentor Graphics John Shields, Mentor Graphics Ken Willis, Cadence Design Systems Kumar Lance Wang, Cadence Design Systems Luis Boluna, Cisco Systems * Michael Mirmak, Intel Corp. * Mike LaBonte, Cisco Systems Mike Steinberger, SiSoft * Mustansir Fanaswalla, Xilinx Patrick O'Halloran, Tiburon Design Automation Paul Fernando, NCSU * Radek Biernacki, Agilent (EESof) * Randy Wolff, Micron Technology Ray Comeau, Cadence Design Systems Richard Mellitz, Intel Richard Ward, Texas Instruments * Sam Chitwood, Sigrity Sanjeev Gupta, Agilent Shangli Wu, Cadence Design Systems * Sid Singh, Extreme Networks Stephen Scearce, Cisco Systems Steve Pytel, Ansoft Syed Huq, Cisco Systems Syed Sadeghi, ST Micro * Terry Jernberg, Cadence Design Systems Todd Westerhoff, SiSoft Vikas Gupta, Xilinx Vuk Borich, Agilent * Walter Katz, SiSoft Zhen Mu, Cadence Design Systems ----- Opens: -------------------------- Call for patent disclosure: - No one declared a patent. ------------- Review of ARs: - Walter will propose a question for Arpad to distribute to the reflector to start discussion before the next meeting. - Done - David Banas report Xilinx position on LTI assumption for SerDes - No update - Arpad: Write parameter passing syntax proposal (BIRD draft) for *-AMS models in IBIS that is consistent with the parameter passing syntax of the AMI models - TBD - TBD: Propose a parameter passing syntax for the SPICE - [External ...] also? - TBD - Arpad: Review the documentation (annotation) in the macro libraries. - Deferred until a demand arises or we have nothing else to do ------------- New Discussion: Discussion of EMD poll questions: - Arpad: There was only one response to the emailed questions - Radek: Discussion is driven mostly by the EDA vendors - Michael M: The questions may have been slightly misphrased - Better questions: a) What are the top problems you are encountering b) What is your ideal solution - Is the problem netlisting, module definition, or extending SPICE? - Michael M: We also need to address system level netlists - Need to describe buffers - IBIS does not have "knobs" for changing settings - AMS has limitations in areas like package modeling - A generic SPICE language would help: - It would have to be more powerful than Berkeley SPICE - It would need better controlled sources - Walter: SPICE with EFGH & Laplace would take care of interconnect - EFGH with formulas would be needed - Behavioral EFGH could be simple enough - This might work easily in most simulators - Arpad: Is Berkeley SPICE public domain? - We need only the manual, not the source code - Walter: Downloaded the manual recently - Not Berkeley SPICE+ - We don't want transistors - Arpad: We asked Synopsys if we could use their syntax - They didn't mind, but reserved the right to change the syntax any time - Michael M: Berkeley SPICE must be extended to allow alphabetic node names - Some legal agreement is needed to get the Berkeley SPICE source code - Bob: What does behavioral SPICE mean? - Michael M: Non transistor level - Rich Mellitz goes through examples of behavioral SPICE modeling - The presentation is not brand specific, but far beyond Berkeley SPICE - Walter: TD simulation of serdes is trivial to implement as constant impedance with voltage that changes over time - Performance with transistor models is very bad - Arpad: Do we need a trigger capability? - Michael M: Not required for this application - Walter: Registers create delays to trigger tap levels - Michael M: Proprietary SPICE tools have time elements that make it easy. - Arpad: Interconnect would not need this - Walter: Behavioral TX (not interconnect) needs time-variant elements - Arpad: Are we creating only interconnect SPICE? - Walter: We need 2 levels of the same language - One level only supports interconnect - A few additional elements support buffer models - Mike L: Time triggered sources have been very handy, but not for interconnect - Sam: We are only interested in interconnect models - Bob: The proposal is called "Electrical Module Description" - Modules may be interconnect or small memory boards - Arpad: Same syntax can describe any size module - Controllable buffers would be a solution - Interconnect is also needed - Arpad: Coming up with something totally new makes no sense - Sam: Agree - Buffer descriptions tend to be targeted for some particular tool - All we need is a wrapper to contain the various languages - Arpad: Do we need only the [External Circuit] syntax? - Mike L: Sam is asking for a new interconnect language - Buffers can be in wrappers - Allowing only 3 content types for [External Circuit] has been a problem - Bob: More can be added - Walter: We should have a language that can be converted to any other - Bob: We might go with whichever company grants permission to use their syntax - There is the problem that they could change the reference - Arpad: With a wrapper we need not be concerned about the language - Arpad showed an example [External Circuit] - Walter: D-A conversion is not needed - Arpad: [External Circuit] could be used for package model - John: We don't have enough good examples to show how [External Circuit] can be used - Walter: EMD is like EBD where everything is an [External Circuit] - Arpad: Is the [External Circuit] language set sufficient? - Walter: SPICE is not enough - Mike: It would be good for an [External Circuit] to have multiple language views - Arpad: We can expand Corners to cover that - Arpad: Can we get a prototype for EBD with [External Circuit]? - Walter: Already done, IBIS SPICE - Does this solve the problems we want to solce? - We will see next week AR: Walter prepare "IBIS SPICE" example AR: Arpad create example of EBD with [External Circuit] Next meeting: 22 July 2008 12:00pm PT -----------